1. Field of the Invention
The present invention relates to semiconductor fabrication, in particularly to a semiconductor device with a super junction structure and a method for fabricating the same.
2. Description of the Related Art
A vertical double diffused metal-oxide-semiconductor field effect transistor (VDMOSFET) conventionally comprises a P-N junction formed by an N-type epitaxial drift region and a p-type base doping region overlying the N-type epitaxial drift region. A withstand voltage capacity of the VDMOSFET is determined by a maximum voltage which is sustained by the P-N junction. For high voltage VDMOSFET semiconductor device, a doping concentration of the N-type epitaxial drift region is needed to be reduced and a thickness of the N-type epitaxial draft region is needed to be increased. The above methods for improving the withstand voltage capacity of the semiconductor device correspondingly increase an on-state resistance (Ron) of the semiconductor device. The on-state resistance (Ron), however, is limited by the doping concentration and the thickness of the N-type epitaxial drift region. Therefore, a VDMOSFET having a super-junction structure can thus increase a doping concentration of the N-type epitaxial drift region and reduce an on-state resistance (Ron) of the VDMOSFET at the same time.
Conventionally, a disclosed multi-epi technology (i.e. COOLMOS™) is applied for fabricating the super-junction structure. The multi-epi technology comprises the repeating of processing steps including forming an epitaxial layer, implanting P-type dopants into the epitaxial layer, and diffusing the P-type dopants in the epitaxial layer for several times to form the super-junction structure. Thus, the multi-epi technology has disadvantages such as many fabrication steps and high fabrication costs, and a size of the semiconductor device comprising the super-junction structure formed by the conventional multi-epi technology cannot be reduced easily.